Architectural Adaptation for Power and Performance

Modern computer architectures represent design tradeoffs involving a large number of variables in a very large design space. Choices related to organization of major system blocks (CPU, cache, memory, I/O) do not work well across different applications. The performance and power variation across applications and against changing data set in a given application can easily be an order of magnitude. Architectural adaptation provides an attractive means to ensure high performance and low power. Adaptable architectural components support multiple mechanisms that can be tailored to application needs. In this paper, we show the benefits of architectural adaptation for power and performance using the cache memory as an example. Dynamic L0 cache management selects either L0 cache or L1 cache for instruction fetch. It reduces average power consumption in instruction cache by 29.5% with only 0.7% performance degradation. Dynamic fetch size profiling changes cache fetch size at run-time to improve locality utilization. It improves average benchmark performance by 15%.